Manufacturability-aware physical integrated circuit (IC) design processes, which take into account such factors as yield and reliability, are becoming increasingly important aspects in bridging the gap between what is designed and what is actually produced or fabricated. This disconnect between design and production is often attributable to physical layout patterns (or configurations), also referred to herein as problematic layout patterns, being susceptible to various processing issues related to the manufacturing processes being employed. For instance, ICs are often fabricated using one or more deposition-based, modification-based (e.g., doping, implantation, etc.), patterning-based (e.g., lithography), removal-based (e.g., etching, planarization, etc.), and/or the like manufacturing steps, which are prone to various processing fluctuations, such as bridging, necking, notching, pinching, stressing, and the like, as well as other parametric design marginalities. Beyond affecting yield and reliability, these processing fluctuations also affect the electrical characteristics and, thereby, performance (e.g., timing yields, maximum operating frequencies, etc.) of the IC designs or, more specifically, the interconnects defined by (or within) the design. This is due, in part, to the dimensional variations (e.g., widening, narrowing, etc.) exhibited by at least some of the interconnects (or at least portions thereof) that result from the processing fluctuations. For instance, widening and/or narrowing of an interconnect can cause resistance, capacitance, and/or inductance (RCL) changes, which further effect the performance of the interconnect, such as its timing characteristic (e.g., RCL delay). It is, therefore, desirable to be able to identity, characterize, and remove these problematic layout patterns, as well as to replace them with more reliable, better performing, yield-friendly configurations.
Traditionally, however, design verification processes focusing on the electrical characteristics and, thereby, performance of an IC design have aggregated towards performing timing analysis on the logic design of the IC design in order to estimate one or more timing characteristics of the IC design, such as worst-case and best-case delays. As critical dimensions in the physical IC designs have rapidly scaled smaller and smaller, increased parametric variability of the IC designs has given rise to an increasing number of significant and independent sources of variation in the manufacture of the physical IC design. Consequently, this rise in potential sources of variation has lead to exponential complexity for traditional static timing analysis methodologies. One solution to this problem is path-based statistical timing analysis, in which the probability distribution of the performance of a chip is computed in a single analysis, simultaneously taking into account all possible sources of variation. Such probabilistic methods are often dependent upon restricting the sources of variation to smaller numbers, but conventional algorithms attempt to address the exponential complexity in the dimensionality of the process space. These design verification processes are very computationally intensive, requiring relatively large amounts of computing power and memory resources. Further, these processes are computationally intensive, not to mention, have relatively long “run-times.” In competitive environments like the semiconductor industry, design cycles need to be as short as feasibly possible, and lengthy design verification processes only burden such efforts.
Furthermore, design verification must compensate for the physical effects of fabricating an IC design. This is because performance is dependent not only upon the logic design itself, but also upon the physical implementation, juxtaposition, and signal routing characteristics affecting performance. As such, feature-based RCL extraction becomes evermore critical, especially given the dimensional variations exhibited by at least some IC design features that result from processing fluctuations characteristic to manufacturing problematic layout patterns. Given the repeatability of these patterns, conventional design constraint definitions (whether extracted or simply designer-defined) stand to be greatly augmented by one or more multi-dimensional pattern matching techniques capable of quickly identifying problematic layout patterns and accounting for their electrical characteristic and, thereby, performance effects on timing closure determinations.
A need, therefore, exists for methodology that facilitates efficient design verification tools capable of identifying and accounting for the performance effects of problematic layout patterns in timing analysis determinations. There exists a particular need for methodology enabling the identification and accounting for problematic layout patterns via multi-dimensional pattern matching technology.